The present invention relates generally to digital-to-analog converters (DACs) and particularly to current switching DACs having a sampled output.
A DAC consists essentially of a set of analog current-steering switches each controlled by one of the DAC's digital inputs. In an n-bit current switching DAC the digital input is an n-bit binary number, or word, and each bit has a corresponding weighted current. The weighted currents I.sub.1. . . , I.sub.n are related by I.sub.k =2.sup.k-1 I, where k is an integer in the range of 1.ltoreq.k.ltoreq.n, where the k.sup.th weighted current corresponds to the k.sup.th bit of the n-bit binary word and where k=1 corresponds to the least significant bit. For each bit which is equal to "1" a corresponding weighted current is coupled to the output of the DAC and for each bit which is equal to "0" a corresponding weighted current is not coupled to the output of the DAC. In this manner the current at the output of the DAC is the sum of the individual weighted currents coupled to the output of the DAC and the magnitude is proportional to the n-bit word input to the DAC.
All DACs have an inherent limitation that may cause troublesome transients or glitches to be superimposed on the DAC output signal. When a new input word is applied to the DAC input to replace the previous word, proper operation of the DAC requires a simultaneous change of logic states on all digital inputs. In practical digital systems, however, the arrival of logic signals at the DAC inputs will always be somewhat skewed, mainly due to non-uniform delays in the individual logic signal source circuitry and interconnecting wiring. Further, individual switch cells may turn on faster than other switch cells, turn on faster than off or off faster than on, or in some cases a mixture of both. During the time when logic inputs are changing (skew time), the analog portion of the DAC will produce a glitch.
The glitch will be most severe at the time of the major carry--when all logic inuts are changing. For a DAC the single-count transition between 011 . . . 111 and 100 . . . 000 could produce an intermediate logic state (e.g., the worst case) of 000 . . . 000 or 111 . . . 111 during the skew interval. This momentary logic input will force the analog output of the DAC to slew towards either voltage extreme for the duration of the skew time. The higher the rate of succession of digital words (i.e., the shorter the duration of each word at the DAC's input) the more significant the glitch becomes.
This skew time (caused by unequal turn-on/off times and bit transmission delays) can be minimized if all logic bits are loaded into a clocked storage register before transfer to the DAC. The simultaneous transfer of all bits into the DAC will limit skew times to those of the register and the DAC switches. typically the register consists of a set of latches or master-slave flip-flops inserted between the digital inputs and the analog switches and is usually located in the immediate physical vicinity of the analog switches, preferably on the same monolithic chip. The DAC digital data inputs drive the data inputs of the master-slave flip-flops and the flip-flop outputs in turn drive the analog switches. The clock inputs of the flip-flops are all driven by a common clock signal whose phase is chosen so that its positive transition occurs prior to the most advanced data transition (the master-slave flip-flops are assumed to be positive-edge-triggered). The positive transition in the clock signal results in a transition in the flip-flop output signals which updates the output signals to become copies of the flip-flop input data. Because the flip-flops are all clocked by a common clock signal, the inputs to the analog switches occur simultaneously with negligible skew between the inputs and the DAC's output current controlled by the analog switches changes smoothly from a value representing one digital word to a value representing the next digital word.
However, this method of glitch removal has a drawback which may largely defeat the original purpose of the flip-flops, i.e., the removal of unwanted glitches from the DAC output signal. Since the flip-flops are positive-edge-triggered, the negative going edge of the clock represents an unavoidable "unused" transition of the clock signal. Due to the finite switching speeds of the flip-flops this unused clock transition cannot be moved arbitrarily close to the active transitions, but must occur somewhere near the center of the word interval, i.e., in the center of the interval between two active transitions. Consequently the unused clock transition will occur after the analog switch has settled and the DAC output current is being utilized. Due to crosstalk between the flip-flops and the analog switches and elsewhere on the chip, the unused clock transition will cause a disturbance (glitch) in the DAC output (analog output).
An additional spike or glitch may be generated in the DAC output when the DAC input changes state causing an internal switching in the DAC. The internal switching creates a transient overshoot or undershoot at the leading or trailing edge of an output transient. The amplitude of the glitch can be significant when compared to the size of a step being made. For low bandwidth (slow) systems the time that the glitch exist may be very short compared to the total duration of the step and conventional low pass filtering may be utilized to satisfactorily remove the glitches. In high bandwidth (fast) systems, where the glitch may comprise a significant portion of the step duration, other means must be employed to eliminate the glitch. One such means comprises a sample and hold circuit in which the output of the DAC is sampled just prior to the end of the word interval, when the output has stabilized, and this value held during the glitch of the next step. A new sample is then taken after the DAC output has settled to the new value in the next word interval.
Use of sample and hold systems may present several significant drawbacks. One limitation in a sample and hold system is the minimum acquisition time (i.e., the time required for the previous value to become the new value). The time to switch from sample to hold must be fast enough to decouple the sample and hold circuit from the following glitch. The decay rate of the storage element, typically a capacitor, during the hold period must be small enough to produce negligible error. Further, feedthrough from the sample switch to the stroage element may generate spiking much larger than the size of the steps in the DAC output thereby defeating the purpose of the sample and hold circuit.